EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 9

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Production Devices for Stratix IV GX Devices
Table 2. Maximum Data Rate Specification in ALTGX Functional Modes Impacted by ×N Clock Line Timing Issue (Part 2
of 2)
March 2011 Altera Corporation
Basic (PMA
Direct) ×N
(OIF) CEI
PHY Interface
Notes to
(1) Contact Altera Technical Support for guidance about V
(2) The ATX PLL (6G) is not available in C4 and I4 speed grades in Stratix IV GX devices.
Functional
ALTGX
Mode
Table
2:
ATX PLL (6G)
ATX PLL (6G)
TX PLL Type
CMU PLL
Up to ×17
Up to ×12
Bonding
> ×17
> ×12
—
Speed Grade
C2/C3/I3
C2/C3/I3
All
All
CCL_GXB
All
All
All
(2)
(2)
/V
Supported Data Rates
C CT
/V
Supply Level
C CR
V
1.2 ± 0.05
1.2 ± 0.05
V
CCT
CCL_GXB
(V)
power estimation at the elevated 1.2V supply level.
1.1
1.1
1.1
1.1
1.1
/V
(1)
CCR
/
Rate (Gbps)
Max Data
6.375
3.25
5.0
6.5
6.5
5.0
6.5
Errata Sheet for Stratix IV GX Devices
Bonded channels must be
contiguous. You must use
the CMU PLL in the middle
transceiver block. For more
information, refer to
Figure
Bonded channels must be
located in two adjacent
transceiver blocks. You
must use the ATX PLL
located between these two
transceiver blocks.
You must use ATX L1 PLL
(6G) for left-side bonding.
You must use ATX R1 PLL
(6G) for right-side bonding.
For more information, refer
to
You must use the 6G ATX
PLL adjacent to the
transceiver block where the
channels are located.
Placement Restrictions
Figure
6.
7.
—
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