EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 38

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 8 of 8)
April 2011 Altera Corporation
Interface speed
(PMA Direct)
Digital reset pulse
width
Notes to
(1) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) You must use the 1.2-V RXV
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization,
(7) The rate matcher supports only up to
(8) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(9) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode.
(10) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(11) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the "Left/Right PLL
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the link. You
(15) Pending Characterization.
(16) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels physically
frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to the
Dynamic Reconfiguration in Stratix IV Devices
jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive the minimum eye
opening requirement with Receiver Equalization enabled.
Refer to
Requirements in Basic (PMA Direct) Mode" section in the
can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about clocking requirements
in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the
located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any
two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
Description
Symbol/
Table
Figure 1–2 on page
1–24:
Conditions
ICM
1–31.
—
—
setting if the input serial data standard is LVDS.
±
300 ppm.
–1 Industrial Speed Grade
Min
50
chapter.
Typ
—
Transceiver Clocking in Stratix IV Devices
Max
325
Minimum is two parallel clock cycles
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Transceiver Clocking in Stratix IV Devices
Min
50
–2 Industrial Speed
Figure 1–2 on page
Grade
Typ
—
chapter.
Max
325
Figure 1–2 on page
Figure 1–3 on page
1–31.
Min
50
–3 Industrial Speed
chapter.
Grade
Typ
1–31.
—
1–31.
Max
325
1–30
MHz
Unit
—