EP2S180F1020C3 Altera, EP2S180F1020C3 Datasheet - Page 87

• Manufacturer Part Number: EP2S180F1020C3
• Description: IC STRATIX II FPGA 180K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1020C3

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 742
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1787

Figure 2–53. Input Timing Diagram in DDR Mode
Altera Corporation
May 2007
Input To
Logic Array
Data at
input pin
CLK
B0
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time.
Figure 2–55
A0
B1
A0
B0
A1
shows the DDR output timing diagram.
Figure 2–54
B2
A1
B1
A2
B3
A2
B2
shows the IOE configured for DDR output.
A3
B4
A3
B3
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–79