EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 10
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–11. OCT Without Calibration Resistance Tolerance Specifications for Stratix IV Devices
April 2011 Altera Corporation
25-Ω R
3.0 and 2.5
25-Ω R
1.8 and 1.5
25-Ω R
1.2
50-Ω R
3.0 and 2.5
50-Ω R
1.8 and 1.5
50-Ω R
1.2
100-Ω R
2.5
Symbol
S
S
S
S
S
S
D
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change.
without calibration resistance tolerance to PVT changes.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–12
calibration. Use
and
Equation 1–1. OCT Variation Without Re-Calibration
Notes to
(1) The R
(2) R
(3) ΔT is the variation of temperature with respect to the temperature at power-up.
(4) ΔV is the variation of voltage with respect to the V
(5) dR/dT is the percentage change of R
(6) dR/dV is the percentage change of R
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal differential
termination (100-Ω setting)
and V
Equation 1–1
SCAL
Equation
CCIO
OCT
is the OCT resistance value at power-up.
Description
.
value calculated from
lists OCT variation with temperature and voltage after power-up
1–1:
Table 1–12
to determine the OCT variation without re-calibration.
R
OCT
Equation 1–1
to determine the OCT variation after power-up calibration
=
V
V
V
V
CCIO
CCIO
CCIO
CCIO
SCAL
SCAL
R
SCAL
V
V
V
Conditions
with temperature.
with voltage.
= 3.0 and 2.5 V
= 1.8 and 1.5 V
CCIO
= 3.0 and 2.5 V
= 1.8 and 1.5 V
CCIO
CCIO
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
shows the range of OCT resistance with the variation of temperature
⎛
⎝
= 1.2 V
= 1.2 V
= 2.5 V
1
+
CCIO
〈
dR
------ -
at power-up.
dT
×
(Note
ΔT
〉
±
± 30
± 30
± 35
± 30
± 30
± 35
± 25
Table 1–11
C2
〈
1), (2), (3), (4), (5),
dR
------ -
dV
Resistance Tolerance
×
ΔV
C3,I3
〉
lists the Stratix IV OCT
± 40
± 40
± 50
± 40
± 40
± 50
± 25
⎞
⎠
(6)
C4,I4
± 40
± 40
± 50
± 40
± 40
± 50
± 25
Unit
%
%
%
%
%
%
%
1–8