EP1S80F1020C6N Altera, EP1S80F1020C6N Datasheet - Page 105
EP1S80F1020C6N
Manufacturer Part Number
EP1S80F1020C6N
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S80F1020C6N
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S80F1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–54. Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs
Altera Corporation
July 2005
scandata
scanaclr
scanclk
f
REF
÷n
Counters and Clock
Delay Settings are
Programmable
f
Δt
PLL reconfiguration data is shifted into serial registers from the logic
array or external devices. The PLL input shift data uses a reference input
shift clock. Once the last bit of the serial chain is clocked in, the register
chain is synchronously loaded into the PLL configuration bits. The shift
circuitry also provides an asynchronous clear for the serial registers.
For more information on PLL reconfiguration, see AN 282: Implementing
PLL Reconfiguration in Stratix & Stratix GX Devices.
Programmable Bandwidth
You have advanced control of the PLL bandwidth using the
programmable control of the PLL loop characteristics, including loop
filter and charge pump. The PLL’s bandwidth is a measure of its ability to
track the input clock and jitter. A high-bandwidth PLL can quickly lock
onto a reference clock and react to any changes in the clock. It also will
allow a wide band of input jitter spectrum to pass to the output. A low-
bandwidth PLL will take longer to lock, but it will attenuate all high-
frequency jitter components. The Quartus II software can adjust PLL
characteristics to achieve the desired bandwidth. The programmable
PFD
÷m
Charge
Pump
Δt
Loop
Filter
VCO
Stratix Device Handbook, Volume 1
All Output Counters and
Clock Delay Settings can
be Programmed Dynamically
÷g
÷e
÷l
Stratix Architecture
Δt
Δt
Δt
2–91
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