EP2S130F1020C3N Altera, EP2S130F1020C3N Datasheet - Page 217

• Manufacturer Part Number: EP2S130F1020C3N
• Description: IC STRATIX II FPGA 130K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1020C3N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2159

Altera Corporation
April 2011
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Notes to
(1)
(2)
Column I/O Output
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
1.5-V HSTL
Class I
1.5-V HSTL
Class II
1.2-V HSTL
LVPECL
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins
Standard I/O
Standard
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
Table
Note (1)
(2)
5–81:
Maximum DCD for Non-DDIO Output
-3 Devices
190
140
125
185
105
100
170
80
90
70
80
80
85
50
55
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
-4 & -5 Devices
220
175
155
110
215
135
130
115
100
110
110
115
80
80
-
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–81