EP2S130F1020I5 Altera, EP2S130F1020I5 Datasheet - Page 186
EP2S130F1020I5
Manufacturer Part Number
EP2S130F1020I5
Description
IC STRATIX II FPGA 130K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1020I5
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Timing Model
5–50
Stratix II Device Handbook, Volume 1
Note to
(1)
Clock skew adder
EP2S15, EP2S30,
EP2S60
Clock skew adder
EP2S90
Clock skew adder
EP2S130
Clock skew adder
EP2S180
Table 5–68. Clock Network Specifications
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Table
(1)
(1)
(1)
(1)
Name
5–68:
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified.
two clock networks driving registers in the IOE.
Description
Table 5–68
specifies the clock skew between any
Min
Typ
Altera Corporation
±100
±110
±125
±150
Max
±50
±55
±63
±75
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
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