EP2S180F1020C5N Altera, EP2S180F1020C5N Datasheet - Page 120
EP2S180F1020C5N
Manufacturer Part Number
EP2S180F1020C5N
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1020C5N
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1885
EP2S180F1020C5N
EP2S180F1020C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1020C5N
Manufacturer:
ALTERA
Quantity:
745
Part Number:
EP2S180F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Configuration
3–6
Stratix II Device Handbook, Volume 1
The PLL_ENA pin and the configuration input pins
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSEL input pin selects which input buffer is used. The 3.3-
V/2.5-V input buffer is powered by V
buffer is powered by V
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by V
A logic high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to
comply with the logic levels driven out of the configuration device or
MAX
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSEL to a logic low; you can set the V
bank that contains the configuration inputs to any supported voltage. If
nSTATUS
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK
as an input)
CS
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
®
(when used
II/microprocessor.
Pin
(when
3.3/2.5-V input buffer is
selected. Input buffer is
powered by V
VCCSEL = LOW (connected
CCIO
CCINT
.
Table 3–4
to GND)
and must be hardwired to V
C C P D
.
shows the pins affected by VCCSEL.
CCPD,
while the 1.8-V/1.5-V input
1.8/1.5-V input buffer is
selected. Input buffer is
powered by V
bank.
VCCSEL = HIGH (connected
(Table
Altera Corporation
CCIO
to V
CCPD
3–4) have a
C C I O
CCPD
of the I/O
or ground.
)
of the I/O
May 2007
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