EP1S80F1508C7 Altera, EP1S80F1508C7 Datasheet - Page 75

• Manufacturer Part Number: EP1S80F1508C7
• Description: IC STRATIX FPGA 80K LE 1508-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80F1508C7

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 1203
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1442

Altera Corporation
July 2005
Pipeline/Post Multiply Register
The output of 9 × 9- or 18 × 18-bit multipliers can optionally feed a register
to pipeline multiply-accumulate and multiply-add/subtract functions.
For 36 × 36-bit multipliers, this register will pipeline the multiplier
function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator, a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplier. You can configure the adder/output block to use output
registers in any mode, and must use output registers for the accumulator.
The system cannot use adder/output blocks independently of the
multiplier.
Figure 2–34
shows the adder and output stages.
Stratix Device Handbook, Volume 1
Stratix Architecture
2–61