EP2S130F780C5 Altera, EP2S130F780C5 Datasheet - Page 26
EP2S130F780C5
Manufacturer Part Number
EP2S130F780C5
Description
IC STRATIX II FPGA 130K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F780C5
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1462
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F780C5N
Manufacturer:
ALTERA
Quantity:
591
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Adaptive Logic Modules
Figure 2–13. ALM in Shared Arithmetic Mode
Note to
(1)
2–18
Stratix II Device Handbook, Volume 1
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Figure
datae0
datae1
datab
dataa
datad
datac
2–13:
Adder trees can be found in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in
partial carry (C[2..0]) is obtained using the LUTs, while the result
(R[2..0]) is computed using the dedicated adders.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
Figure
carry_out
carry_in
2–14. The partial sum (S[2..0]) and the
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Altera Corporation
May 2007
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