EP2S90F1508I4N Altera, EP2S90F1508I4N Datasheet - Page 88
![IC STRATIX II FPGA 90K 1508-FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S90F1508I4N
Manufacturer Part Number
EP2S90F1508I4N
Description
IC STRATIX II FPGA 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1508I4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
902
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F1508I4N
Manufacturer:
ALTERA
Quantity:
586
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I/O Structure
Figure 2–54. Stratix II IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
(3)
2–80
Stratix II Device Handbook, Volume 1
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports
of the DDIO megafunction.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–54:
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Chip-Wide Reset
Output Register
Output Register
OE Register
OE Register
ENA
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
ENA
Q
Q
Q
Q
Notes
Used for
DDR, DDR2
SDRAM
clk
Open-Drain Output
(1),
Drive Strength
Pin Delay
(2)
Output
Control
OE Register
t CO Delay
V CCIO
V CCIO
Altera Corporation
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
May 2007
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