EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 171

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 4–65. Input Timing Diagram in DDR Mode
Altera Corporation
February 2005
Input To
Logic Array
Data at
input pin
CLK
A'
B'
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×
while the other output register clocks the second bit out on the clock low
time.
shows the DDR output timing diagram.
2 rate. One output register clocks the first bit out on the clock high time,
A0
Figure 4–66
B1
A1
B2
shows the IOE configured for DDR output.
A1
B1
A2
B3
A2
B2
A3
Stratix GX Device Handbook, Volume 1
B4
A3
B3
Stratix GX Architecture
Figure 4–67
4–105