EP1SGX40DF1020C5 Altera, EP1SGX40DF1020C5 Datasheet - Page 93
EP1SGX40DF1020C5
Manufacturer Part Number
EP1SGX40DF1020C5
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX40DF1020C5
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX40DF1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
February 2005
Table 4–4. M4K RAM Block Configurations (Simple Dual-Port)
Table 4–5. M4K RAM Block Configurations (True Dual-Port)
Read Port
256
128
256
128
512
512
4K
2K
1K
×
×
×
×
×
×
×
256
256
×
×
512
512
4K
2K
1K
Port A
1
2
4
16
32
18
36
8
9
×
×
×
×
×
×
×
16
18
1
2
4
8
9
4K 1
v
v
v
v
v
v
2K × 2
4K × 1
v
v
v
v
v
v
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
widths.
configurations.
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
v
v
v
v
v
1K ° 4 512 ° 8 256 ° 16
v
v
v
v
v
v
Tables 4–4
2K × 2
v
v
v
v
v
v
v
v
v
v
v
and
1K × 4
v
v
v
v
v
4–5
v
v
v
v
v
v
Write Port
summarize the possible M4K RAM block
512 × 8
Port B
v
v
v
v
v
128 ° 32 512 ° 9 256 ° 18
Stratix GX Device Handbook, Volume 1
v
v
v
v
v
v
256 × 16
v
v
v
v
v
v
v
v
Stratix GX Architecture
512 × 9
v
v
v
v
v
256 × 18
128 ° 36
v
v
v
v
v
4–27
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