EP1SGX40GF1020I6N Altera, EP1SGX40GF1020I6N Datasheet - Page 126
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EP1SGX40GF1020I6N
Manufacturer Part Number
EP1SGX40GF1020I6N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40GF1020I6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Digital Signal Processing Block
Figure 4–34. Simple Multiplier Mode
Note to
(1)
4–60
Stratix GX Device Handbook, Volume 1
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
Figure
shiftout B
4–34:
shiftin B
shiftout A
ENA
ENA
D
D
CLRN
CLRN
DSP blocks can also implement one 36
mode. DSP blocks use four 18
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36
that is normally a multiplier-result-output register as a pipeline stage for
the 36
mode.
shiftin A
signa (1)
signb (1)
×
Q
Q
clock
36-bit multiplier. In 36
ena
aclr
×
36-bit multiplier.
ENA
D
Figure 4–35
CLRN
×
36-bit mode, the device can use the register
Q
×
18-bit multipliers combined with
shows the 36
×
36-bit multiplier in multiplier
ENA
D
CLRN
Q
×
36-bit multiply
Altera Corporation
February 2005
Data Out
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