EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 308

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C4N

Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
0
August 2007
v4.4
May 2007 v4.3
Table 4–118. Document Revision History (Part 2 of 5)
Document
Date and
Version
Changed 1.875 KHz to 1.875 MHz in Table 4–19,
Removed note “The data in this table is preliminary.
Altera will provide a report upon completion of
characterization of the Stratix II GX devices.
Conditions for testing the silicon have not been
determined.” from each table.
Removed note “The data in Tables xxx through xxx
is preliminary. Altera will provide a report upon
completion of characterization of the Stratix II GX
devices. Conditions for testing the silicon have not
been determined.” in the clock timing parameters
sections.
Updated clock timing parameter Tables 4–63
through 4–78 (Table 4–75 was unchanged).
Updated Table 4–21 and added new Table 4–22.
Updated:
Added note to Table 4–50.
Added:
Added the “Referenced Documents” section.
XAUI Receiver Jitter Tolerance section.
Table 4–6
Table 4–16
Table 4–19
Table 4–49
Table 4–52
Table 4–107
Figure 4–3
Figure 4–4
Figure 4–5
Changes Made
Summary of Changes

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