EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 35

no-image

EP1S40F1020C5

Manufacturer Part Number
EP1S40F1020C5
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40F1020C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2089

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EP1S40F1020C5
Manufacturer:
XILINK
Quantity:
5 510
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA30
Quantity:
113
Part Number:
EP1S40F1020C5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S40F1020C5
0
Part Number:
EP1S40F1020C5ES
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
TriMatrix
Memory
Altera Corporation
July 2005
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM blocks. Although these memory blocks are different, they
can all implement various types of memory with or without parity,
including true dual-port, simple dual-port, and single-port RAM, ROM,
and FIFO buffers.
RAM blocks.
Maximum
performance
True dual-port
memory
Simple dual-port
memory
Single-port memory
Shift register
ROM
FIFO buffer
Byte enable
Parity bits
Mixed clock mode
Memory initialization
Simple dual-port
memory mixed width
support
True dual-port
memory mixed width
support
Power-up conditions
Register clears
Mixed-port read-
during-write
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Table 2–3
Outputs cleared
Input and output
registers
Unknown
output/old data
M512 RAM Block
(32 × 18 Bits)
shows the size and features of the different
v
v
v
v
v
v
v
v
v
(1)
Stratix Device Handbook, Volume 1
Outputs cleared
Input and output
registers
Unknown
output/old data
M4K RAM Block
(128 × 36 Bits)
(1)
v
v
v
v
v
v
v
v
v
v
v
v
Stratix Architecture
unknown
Output registers
Unknown output
Outputs
(4K × 144 Bits)
M-RAM Block
(1)
v
v
v
(2)
v
v
v
v
v
v
2–21

Related parts for EP1S40F1020C5