EP1S40F1020I6N Altera, EP1S40F1020I6N Datasheet - Page 119
EP1S40F1020I6N
Manufacturer Part Number
EP1S40F1020I6N
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020I6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Figure 2–59. Stratix IOE Structure
Altera Corporation
July 2005
Logic Array
Output B
Output A
Input B
Input A
OE
Output Register
Output Register
The IOEs are located in I/O blocks around the periphery of the Stratix
device. There are up to four IOEs per row I/O block and six IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–60
Figure 2–61
D
D
Q
Q
shows how a row I/O block connects to the logic array.
shows how a column I/O block connects to the logic array.
CLK
OE Register
OE Register
D
D
Q
Q
Input Register
Input Register
Stratix Device Handbook, Volume 1
D
D
Q
Q
Input Latch
D
ENA
Stratix Architecture
Q
2–105
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