EP1S60F1020C7 Altera, EP1S60F1020C7 Datasheet - Page 54

• Manufacturer Part Number: EP1S60F1020C7
• Description: IC STRATIX FPGA 60K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S60F1020C7

• Number Of Logic Elements/cells: 57120
• Number Of Labs/clbs: 5712
• Total Ram Bits: 5215104
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1434

TriMatrix Memory
Figure 2–21. Left-Facing M-RAM to Interconnect Interface
Notes to
(1)
(2)
2–40
Stratix Device Handbook, Volume 1
Only R24 and C16 interconnects cross the M-RAM block boundaries.
The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6
orientation is clipped across the vertical axis for right-facing M-RAM blocks.
Figure
LABs in Row
M-RAM Boundary
Row Unit Interface
Allows LAB Rows to
Drive Address and
Control Signals to
M-RAM Block
2–21:
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
LAB Interface
Blocks
M512 RAM Block Columns
B1
A1
B2
A2
M-RAM Block
B3
A3
Port B
Port A
Notes
B4
A4
(1),
(2)
B5
A5
B6
A6
Column Interface Block
Allows LAB Columns to
Drive datain and dataout to
and from M-RAM Block
Altera Corporation
LABs in Column
M-RAM Boundary
Column Interface Block
Drives to and from
C4 and C8 Interconnects
July 2005