EP1SGX25FF1020I6N Altera, EP1SGX25FF1020I6N Datasheet - Page 3
EP1SGX25FF1020I6N
Manufacturer Part Number
EP1SGX25FF1020I6N
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25FF1020I6N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25FF1020I6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Overview
Features
Altera Corporation
February 2005
SGX51001-1.0
The Stratix
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
■
Transceiver block features are as follows:
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High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
Programmable differential output voltage (V
and equalization settings for improved signal integrity
Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus
software for reduced power consumption during non-operation
Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
Built-in self test (BIST)
Hot insertion/removal protection circuitry
®
GX family of devices is Altera’s second FPGA family to
Stratix GX Device Data Sheet
1. Introduction to the
OD
), pre-emphasis,
®
II
1–1
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