EP20K400FC672-1 Altera, EP20K400FC672-1 Datasheet - Page 42
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EP20K400FC672-1
Manufacturer Part Number
EP20K400FC672-1
Description
IC APEX 20KE FPGA 400K 672-BGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K400FC672-1
Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
502
Number Of Gates
1052000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K400FC672-1
Manufacturer:
ALTERA
Quantity:
642
APEX 20K Programmable Logic Device Family Data Sheet
42
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect.
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
Row Interconnect
LAB
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Figure 27
shows how a row IOE connects to the
MegaLAB Interconnect
IOE
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
Altera Corporation