EP1S40B956C6N Altera, EP1S40B956C6N Datasheet - Page 103
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C6N
Manufacturer Part Number
EP1S40B956C6N
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA
Quantity:
229
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–53. Clock Switchover Circuitry
Altera Corporation
July 2005
INCLK0
INCLK1
There are two possible ways to use the clock switchover feature.
■
■
SMCLKSW
Use automatic switchover circuitry for switching between inputs of
the same frequency. For example, in applications that require a
redundant clock with the same frequency as the primary clock, the
switchover state machine generates a signal that controls the
multiplexer select input on the bottom of
secondary clock becomes the reference clock for the PLL.
Use the clkswitch input for user- or system-controlled switch
conditions. This is possible for same-frequency switchover or to
switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than ±20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
requiring a system-controlled switchover between frequencies of
operation. You can use clkswitch together with the lock signal to
trigger the switch from a clock that is running but becomes unstable
and cannot be locked onto.
MUXOUT
Sense
Enhanced PLL
Clock
n Counter
State Machine
Switch-Over
Δt
Stratix Device Handbook, Volume 1
Figure
PFD
2–53. In this case, the
Stratix Architecture
CLK0_BAD
CLK1_BAD
Active Clock
CLKLOSS
CLKSWITCH
FBCLK
2–89
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