EP2SGX60EF1152I4N Altera, EP2SGX60EF1152I4N Datasheet - Page 154

• Manufacturer Part Number: EP2SGX60EF1152I4N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2187

Document Revision History
2–146
Stratix II GX Device Handbook, Volume 1
Table 2–42. Document Revision History (Part 4 of 6)
Document
Date and
Version
Updated:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Updated bulleted lists at the beginning of the
“Transceivers” section.
Added reference to the “Transmit Buffer”
section.
Deleted the Programmable V
“Programmable Output Driver” section.
Data Width” heading in Table 2–14.
Deleted “Global & Regional Clock
Connections from Right Side Clock Pins &
Fast PLL Outputs” table.
Updated notes to Tables 2–29 and 2–37.
Updated notes to Figures 2–72, 2–73 and
2–74.
Updated bulleted list in the “Advanced I/O
Standard Support” section.
Changed “PLD Interface” heading to “Parallel
“Transmitter PLLs”
“Transmitter Phase Compensation FIFO
Buffer”
“8B/10B Encoder”
“Byte Serializer”
“Programmable Output Driver”
“Receiver PLL & CRU”
“Programmable Pre-Emphasis”
“Receiver Input Buffer”
“Control and Status Signals”
“Programmable Run Length Violation”
“Channel Aligner”
“Basic Mode”
“Byte Ordering Block”
“Receiver Phase Compensation FIFO
Buffer”
“Loopback Modes”
“Serial Loopback”
“Parallel Loopback”
“Regional Clock Network”
“MultiVolt I/O Interface”
“High-Speed Differential I/O with DPA
Support”
Changes Made
OD
table from the
Summary of Changes
Altera Corporation
October 2007