EP1S40F1020C6N Altera, EP1S40F1020C6N Datasheet - Page 93

• Manufacturer Part Number: EP1S40F1020C6N
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 2–46. Regional Clock Bus
Altera Corporation
July 2005
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Global Clock Network [15..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22 quadrant or half-quadrant
clock resources.
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Figures 2–47
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [21..0]
and
2–48
show the quadrant and half-
Stratix Device Handbook, Volume 1
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Stratix Architecture
2–79