EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 82
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–80
Table 1–67. Glossary (Part 3 of 4)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Letter
S
T
SW (sampling
window)
Single-ended
Voltage
Referenced I/O
Standard
t
TCCS
(channel-to-
channel-
skew)
t
t
t
t
t
t
C
DUTY
FALL
INCCJ
OUTPJ_IO
OUTPJ_DC
RISE
Subject
The period of time during which the data must be valid in order to capture it correctly. The setup
and hold times determine the ideal strobe position within the sampling window:
Timing Diagram
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing:
Single-Ended Voltage Referenced I/O Standard
High-speed receiver and transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including t
clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
High-speed I/O block: Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%).
V
V
OH
OL
0.5 x TCCS
RSKM
Definitions
Sampling Window
V
Bit Time
REF
(SW)
Chapter 1: Device Datasheet for Arria II Devices
RSKM
C
V
/w)
December 2010 Altera Corporation
V
IH(DC)
IL(DC)
0.5 x TCCS
V
V
IH ( AC )
IL(AC )
CO
V
CCIO
V
variation and
SS
Glossary