EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 4

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Page 4
Dynamic Reconfiguration Issue Between PCIe Mode and Any Other
Transceiver Mode
Quartus II Software Incorrect Setting for the Transceiver CDR in All
Modes Except PCIe Mode
Errata Sheet for Arria II GX Devices
Workaround
Solution
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1
1
Use the calibration block clock (cal_blk_clk) for the pll_locked_soft_logic module.
The cal_blk_clk frequency specification ranges from 10 MHz to 125 MHz.
Depending on your cal_blk_clk frequency, set the parameter p_delay_counter in the
pll_locked_soft_logic so that the delay is equal to 100 μs (worst-case transmitter
PLL lock time).
If your application uses dynamic reconfiguration to change the transceiver channel
between PCI Express
may not be initialized correctly, resulting in receiver bit errors.
This problem only affects dynamic reconfiguration between PCIe mode and any other
transceiver mode. Dynamic reconfiguration between any transceiver modes other
than PCIe mode is not affected.
If you see bit errors, apply the reset sequence described in the
Solution.
If you need additional support, file a service request at Altera's mysupport.
The Quartus II software versions up to and including 10.0 SP1 incorrectly set the clock
and data recovery (CDR) unit when the transceiver channel is configured in any
mode except PCIe mode and the CDR is configured to automatic lock mode.
When there are no data transitions on the transceiver data inputs for an extended
period of time (in the ms range), the CDR may keep the rx_freqlocked signal
asserted. The CDR does not return to the lock-to-reference state and incorrect data
may be recovered.
The transceiver channels configured in PCIe mode are NOT affected by this issue.
This issue is fixed in the Quartus II software versions 10.1 and later. Altera
recommends upgrading to the latest Quartus II software and recompiling your
design. For complete details of the solution, refer to the
Additionally, software patches are available for the Quartus II software versions
9.1 SP2 and 10.0 SP1.
To download and install the patch, refer to the
®
Dynamic Reconfiguration Issue Between PCIe Mode and Any Other Transceiver Mode
(PCIe) mode and any other transceiver mode, the transceiver
Transceiver CDR
Transceiver CDR
February 2011 Altera Corporation
Reset Sequence
Solution.
Solution.