EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 37

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 6)
December 2010 Altera Corporation
fixedclk clock frequency
reconfig_clk clock
frequency
Delta time between
reconfig_clks
Transceiver block minimum
power-down
(gxb_powerdown) pulse
width
Receiver
Supported I/O Standards
Data rate
Absolute V
pin
Operational V
receiver pin
Absolute V
pin
Maximum peak-to-peak
differential input voltage V
(diff p-p) before device
configuration
Maximum peak-to-peak
differential input voltage V
(diff p-p) after device
configuration
Minimum differential eye
opening at receiver serial
input pins
V
Receiver DC Coupling
Support
ICM
(2)
Description
Symbol/
MAX
MIN
(14)
MAX
for a receiver
for a receiver
for a
(13)
ID
ID
V
Data Rate > 5 Gbps
V
ICM
ICM
clock frequency
Equalization = 0
Equalization = 0
reconfiguration
DC gain = 0 dB
DC gain = 0 dB
PCIe Receiver
V
V
600 Mbps to
Conditions
Data Rate =
ICM
ICM
= 1.1 V setting
=1.1 V setting
Dynamic
5 Gbps
setting
setting
Detect
= 0.82 V
= 0.82 V
—
—
—
—
—
—
—
—
(3)
(3)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the
Devices
37.5
Min
2.5/
-0.4
600
100
165
—
—
—
—
—
—
—
(2)
1
–C3 and –I3
chapter.
1100 ± 10%
820 ± 10%
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
(1)
6375
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
37.5
Min
2.5/
-0.4
600
165
165
—
—
—
—
—
—
—
Transceiver Architecture for Arria II
(2)
1
–C4 and –I4
1100 ± 10%
820 ± 10%
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
3750
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
Mbps
MHz
MHz
Unit
ms
mV
mV
mV
mV
µs
V
V
V
V
V
V
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