EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 8

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Page 8
M9K RAM Block Lock-Up
Automatic Clock Switchover
Remote System Upgrade
Errata Sheet for Arria II GX Devices
Workarounds
1
The M9K RAM blocks can lock up if the read clock glitches when rden=1, which can
occur if the clock source is not from a phase-locked loop (PLL). In this state, a RAM
block no longer responds to read or write operations and requires an FPGA
reconfiguration to restore operation. The issue occurs in the Read Timer Trigger
circuitry, where a glitchy non-PLL clock may inadvertently freeze the Read Timer
Trigger circuitry, locking the RAM block in its last operation. All RAM block modes
are affected. Memory logic array blocks (MLABs) are not affected.
The workarounds are to add clock-enable logic, an internal PLL, or clock generation
logic (for example, a clock divider). You can add clock-enable logic (internal or
external) to disable the RAM block operation until the clock is stable. You can also
gate the clock internally or externally. If your FPGA resources permit, use an internal
PLL or clock generation logic to ensure a stable clock source at the RAM block input.
This issue will be fixed in production devices.
The automatic clock switchover feature may fail to operate correctly on Arria II GX
devices when the two clocks are running at different frequencies. If both clocks are
running at the same frequency, there is no impact to your design. The following
modes are affected:
■
■
You may observe two possible issues:
■
■
Manual clock switchover mode operates correctly and is not affected by this issue.
There is no planned fix for this issue.
The remote system upgrade feature does not operate correctly when you initiate a
reconfiguration cycle that goes from a factory configuration image to an invalid
application configuration image. In this scenario, the Arria II GX device fails to revert
back to the factory configuration image after a configuration error is detected while
loading the invalid application configuration image. The failure is indicated by a
continuous toggling of the nSTATUS pin.
In correct operation, the Arria II GX device should revert back to the factory
configuration image after a configuration error is detected with the invalid
configuration image.
Automatic
Automatic with manual override
Switchover from inclk0 to inclk1, even though inclk0 is active (and vice-versa)
clkbad[0,1] status signals may glitch, even if the input clocks are active
February 2011 Altera Corporation
M9K RAM Block Lock-Up