EP1S25F672I7 Altera, EP1S25F672I7 Datasheet - Page 140

IC STRATIX FPGA 25K LE 672-FBGA

EP1S25F672I7

Manufacturer Part Number
EP1S25F672I7
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F672I7

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2087

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S25F672I7
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F672I7
Manufacturer:
ALTERA
0
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
Part Number:
EP1S25F672I7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
0
Part Number:
EP1S25F672I7N
0
I/O Structure
2–126
Stratix Device Handbook, Volume 1
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL (clock
inputs)
Differential HSTL (clock
outputs)
Differential SSTL (clock
outputs)
3.3-V GTL
3.3-V GTL+
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
Table 2–32. I/O Support by Bank (Part 1 of 2)
I/O Standard
Table 2–32
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
shows I/O standard support for each I/O bank.
Left & Right Banks
(1, 2, 5 & 6)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Altera Corporation
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
July 2005

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