EP1S30F1020C7N Altera, EP1S30F1020C7N Datasheet - Page 121

no-image

EP1S30F1020C7N

Manufacturer Part Number
EP1S30F1020C7N
Description
IC STRATIX FPGA 30K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F1020C7N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
726
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
32470
# I/os (max)
726
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
32470
Ram Bits
3317184
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F1020C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S30F1020C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F1020C7N
Manufacturer:
ALTERA
0
Part Number:
EP1S30F1020C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–61. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
July 2005
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
Local Interconnect
Figure
Signals from I/O
Interconnect (1)
from Logic Array (2)
R4, R8 & R24
Interconnects
16 Control
I/O Block
2–61:
Control Signals
42 Data &
Interconnect
LAB
LAB Local
16
Vertical I/O Block
C4, C8 & C16
Interconnects
42
LAB
IO_datain[3:0]
Stratix Device Handbook, Volume 1
LAB
Vertical I/O
Block Contains
up to Six IOEs
io_clk[7..0]
Stratix Architecture
I/O Interconnect
2–107

Related parts for EP1S30F1020C7N