EP1S25F672I7N Altera, EP1S25F672I7N Datasheet - Page 93
EP1S25F672I7N
Manufacturer Part Number
EP1S25F672I7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672I7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
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Figure 2–46. Regional Clock Bus
Altera Corporation
July 2005
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Global Clock Network [15..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22 quadrant or half-quadrant
clock resources.
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Figures 2–47
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [21..0]
and
2–48
show the quadrant and half-
Stratix Device Handbook, Volume 1
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Stratix Architecture
2–79
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