EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 301
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
Available stocks
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Part Number
Manufacturer
Quantity
Price
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(1)
(2)
f
f
% spread
t
t
t
t
f
f
f
t
VCO
SS
P L L _ P S E R R
ARESET
ARESET_RECONFIG
RECONFIGWAIT
IN
INPFD
INDUTY
INJITTER
Table 4–110. Enhanced PLL Specifications (Part 2 of 2)
Table 4–111. Fast PLL Specifications (Part 1 of 2)
This is limited by the I/O f
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Name
Name
PLL VCO operating range for –3 and
–4 speed grade devices
PLL VCO operating range for –5 speed
grade devices
Spread-spectrum modulation
frequency
Percent down spread for a given clock
frequency
Accuracy of PLL phase shift
Minimum pulse width on
signal.
Minimum pulse width on the
signal when using PLL reconfiguration.
Reset the PLL after
high.
The time required for the wait after the
reconfiguration is done and the areset
is applied.
Input clock frequency (for -3 and -4 speed
grade devices)
Input clock frequency (for -5 speed grade
devices)
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
MAX
Description
. See
Description
Tables 4–91
≤
2 MHz
scandone
areset
areset
through
goes
4–95
Min
300
300
100
500
0.4
10
for the maximum.
Min
16
16
16
40
Typ
0.5
Typ
0.5
1.0
1,040
Max
840
500
±30
0.6
2
Max
500
717
640
60
ns (p-p)
ns (p-p)
MHz
MHz
Unit
kHz
MHz
MHz
MHz
Unit
ps
ns
ns
us
%
%
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