EP1SGX10DF672C5 Altera, EP1SGX10DF672C5 Datasheet - Page 139
EP1SGX10DF672C5
Manufacturer Part Number
EP1SGX10DF672C5
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C5
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX10DF672C5
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
February 2005
Figure 4–44. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, 4 regional clock lines, and 2 fast
regional clock lines. Multiplexers are used with these clocks to form 8-bit
busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer at the LAB level selects two of the eight row clocks
to feed the LE registers within the LAB. See
fclk[1..0]
Fast Clock
Fast Clock
[3]
[4]
Fast Clock
Fast Clock
Stratix GX Device Handbook, Volume 1
[2]
[5]
Fast Clock
Fast Clock
Figure
[1]
[6]
Stratix GX Architecture
4–45.
Fast Clock
Fast Clock
[0]
[7]
4–73
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