EP3C120F484I7 Altera, EP3C120F484I7 Datasheet - Page 114

• Manufacturer Part Number: EP3C120F484I7
• Description: IC CYCLONE III FPGA 120K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F484I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 283
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 283
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

6–14
Figure 6–6. Cyclone III Device Family HSTL I/O Standard Termination
Figure 6–7. Cyclone III Device Family SSTL I/O Standard Termination
Differential I/O Standard Termination
Cyclone III Device Handbook, Volume 1
Termination
Termination
and without
Calibration
On-Board
OCT with
External
Termination
and without
Termination
Calibration
OCT with
On-Board
External
Cyclone III Device
Family Series OCT
Transmitter
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential
LVPECL.
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
50
50
25
SSTL Class I
HSTL Class I
50
50
50
V REF
50
V REF
50
V REF
50
50
V REF
50
V TT
V TT
V TT
V TT
(Figure 6–8
Receiver
Receiver
Receiver
Receiver
and
Cyclone III Device
Family Series OCT
Figure
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
Transmitter
25
25
Chapter 6: I/O Features in the Cyclone III Device Family
6–9).
V TT
V TT
25
50
HSTL Class II
50
SSTL Class II
50
50
V TT
V TT
50
50
V REF
© December 2009 Altera Corporation
50
50
V REF
Termination Scheme for I/O Standards
50
50
V TT
50
V REF
V REF
V TT
50
V TT
V TT
Receiver
Receiver
Receiver
Receiver