EP1S25F672C7N Altera, EP1S25F672C7N Datasheet - Page 21
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/74/67406/ep1s25f672c7n_sml.jpg)
EP1S25F672C7N
Manufacturer Part Number
EP1S25F672C7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1858
EP1S25F672C7N
EP1S25F672C7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–5. Stratix LE
Altera Corporation
July 2005
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
addnsub
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock &
LAB Carry-In
Select
Carry-In1
Carry-In0
Look-Up
(LUT)
Table
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register’s
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the register is
bypassed and the output of the LUT drives directly to the outputs of the
LE.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
Chain
Carry
Register chain
routing from
previous LE
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
Stratix Device Handbook, Volume 1
Packed
Register Select
ADATA
D
ENA
PRN/ALD
CLRN
Register
Feedback
Q
Programmable
Register
Stratix Architecture
LUT chain
routing to next LE
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Local Routing
Register chain
output
2–7
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