EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 19

• Manufacturer Part Number: EP4CE115F29I8LN
• Description: IC CYCLONE IV FPGA 115K 780-FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE115F29I8LN

• Number Of Logic Elements/cells: 114480
• Number Of Labs/clbs: 7155
• Total Ram Bits: 3888000
• Number Of I /o: 528
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)—Preliminary
© December 2010 Altera Corporation
PLD-Transceiver Interface
Interface speed
(F324 and smaller
package)
Interface speed
(F484 and larger
package)
Digital reset pulse
width
Notes to
(1) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk
(2) The device cannot tolerate prolonged operation at this absolute maximum.
(3) The rate matcher supports only up to ±300 parts per million (PPM).
(4) Supported for the N148, F169, and F324 device packages only.
(5) Supported for the F484, F672, and F896 device packages only. Pending device characterization.
(6) To support CDR PPM tolerance greater than ±300 PPM, you have to implement PPM detector in user logic and configure CDR to Manual Lock mode.
(7) Supported for the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices only.
(8) This specification is only valid for SATA protocol implementation in Basic mode. Pending device characterization.
(9) Time taken until pll_locked goes high after pll_powerdown deasserts.
(10) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode.
(11) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode
(12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode.
(13) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.
frequency is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.
automatic mode
Description
Symbol/
Table
1–21:
(Figure
1–3).
Conditions
—
—
—
Min
25
25
Typ
—
—
C6
156.25
Max
125
Min
25
25
Minimum is 2 parallel clock cycles
Typ
—
—
C7
(Figure
156.25
Max
125
Cyclone IV Device Handbook, Volume 3
1–2), or after rx_freqlocked signal goes high in
Min
25
25
Typ
—
—
C8
156.25
Max
125
1–19
Unit
MHz
MHz