EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 35

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Table 1–34. Transceiver Specifications for Arria II GX Devices (Part 7 of 7)
Digital reset
pulse width
Notes to
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The device cannot tolerate prolonged operation at this absolute maximum.
(3) You must use the 1.1-V RX V
(4) The rate matcher supports only up to ±300 parts per million (ppm).
(5) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(6) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to
(7) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(8) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(9) The rise/fall time is specified from 20% to 80%.
(10) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is
(11) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
Description
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to
you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum
specification listed.
Symbol/
Table
1–34:
Condition
—
ICM
setting if the input serial data standard is LVDS and the link is DC-coupled.
Min
I3
Typ
Max
Min
(Note 1)
Figure
Typ
1–1.
AN 558: Implementing Dynamic Reconfiguration in Arria II
C4
Minimum is 2 parallel clock cycles
Max
Figure
Figure
1–1.
1–2.
Min
C5 and I5
Typ
Max
Devices.
Min
Figure
Typ
C6
1–1.
Max
Unit