EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 79
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EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
Chapter 1: Device Datasheet for Arria II Devices
I/O Timing
Table 1–66. IOE Programmable Delay for Arria II GZ Devices
I/O Timing
December 2010 Altera Corporation
Notes to
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) Minimum offset does not include the intrinsic delay.
Parameter
D1
D2
D3
D4
D5
D6
Table
1–66:
f
Available
Settings
15
15
15
(1)
7
7
6
Table 1–66
Altera offers two ways to determine I/O timing:
■
■
The Microsoft Excel-based I/O Timing provides pin timing performance for each
device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis. The
Quartus II timing analyzer provides a more accurate and precise I/O timing data
based on the specifics of the design after place-and-route is complete.
The Microsoft Excel-based I/O Timing spreadsheet is downloadable from the
Literature: Arria II Devices
Using the Microsoft Excel-based I/O Timing.
Using the Quartus II Timing Analyzer.
Offset
Minimum
0
0
0
0
0
0
lists the IOE programmable delay settings for Arria II GZ devices.
(2)
Industrial
0.462
0.234
1.700
0.508
0.472
0.186
Fast Model
web page.
Commercial
0.505
0.232
1.769
0.554
0.500
0.195
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Maximum Offset
0.795
0.372
2.927
0.882
0.799
0.319
C3
0.801
0.371
2.948
0.889
0.817
0.321
I3
Slow Model
0.857
0.407
3.157
0.952
0.875
0.345
C4
0.864
0.405
3.178
0.959
0.882
0.347
I4
Unit
ps
ps
ps
ps
ps
ps
1–77