EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 7
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EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
XAUI State Machine Failure—Channel 0 Shifted by One Cycle
XAUI State Machine Failure—Channel 0 Shifted by One Cycle
Figure 4. Rate Matcher FIFO Skew
Error Detection CRC Feature
February 2011 Altera Corporation
Correct Channel Alignment
XAUI Protocol Purposes
Skewed Channel 0
XAUI Protocol Purposes
Master channel for
Master channel for
Workaround
1
channel 0
channel 1
channel 2
channel 3
channel 0
channel 1
channel 2
channel 3
In XAUI functional mode, the data out of the channel 0 Rate Match FIFO may be
shifted by one byte with respect to the data of the other three channels. This causes
incorrect idle ordered set conversion, resulting in incorrect received parallel data. This
issue happens only during initialization or receiver channel reset (assertion of
rx_analogreset or rx_digitalreset).
Figure 4
A soft IP solution for this issue is available by contacting Altera.
The Error Detection CRC feature is typically used to detect single event upsets (SEU).
When enabled, the Error Detection CRC feature may cause the memory logic array
block (MLAB) RAM to operate incorrectly in Arria II GX ES devices. Only write
operations in the MLAB RAM blocks are affected.
The Error Detection CRC feature and CRC error flag operate correctly. FPGA
configuration bits are not affected by this issue.
If you do not use Error Detection CRC, no action is required. The MLAB RAM blocks
will operate correctly.
If you enable Error Detection CRC, disabling the Error Detection CRC resolves the
problem.
Also, using M9K RAM blocks or Logic Cells (LCs) instead of MLAB RAM blocks
resolves the problem.
This issue will be fixed in production devices.
K
K
K
K
--
K
K
K
shows the channel skew.
R
R
R
R
K
R
R
R
R
S
D
D
D
D
D
D
D
D
D
D
D
D
D
S
--
--
--
--
D
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
D
D
D
D
--
D
D
D
D
K
T
K
D
T
K
K
A
A
A
A
D
A
A
A
R
R
R
R
R
R
A
R
R
R
R
R
R
R
R
R
K
K
K
K
R
K
K
K
Errata Sheet for Arria II GX Devices
K = Lane Synchronization character
S = Start of packet
T = End of packet
D = Data packet
A = Alignment character
R = Clock Rate Compensation character
Page 7