EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 45

• Manufacturer Part Number: EP2SGX30CF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30CF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1750

Altera Corporation
October 2007
The receiver PLL can also drive the regional clocks and regional routing
adjacent to the associated transceiver block.
global clock resource can be used by the recovered clock.
shows which regional clock resource can be used by the recovered clock.
Figure 2–30. Stratix II GX Receiver PLL Recovered Clock to Global Clock
Connection
Notes to
(1)
(2)
CLK[3..0]
CLK# pins are clock pins and their associated number. These are pins for global
and regional clocks.
GCLK# pins are global clock pins.
Figure
7
1
2
8
2–30:
Notes
GCLK[3..0]
(1),
(2)
GCLK[15..12]
CLK[15..12]
GCLK[4..7]
CLK[7..4]
Stratix II GX Device Handbook, Volume 1
11 5
12 6
Figure 2–30
GCLK[11..8]
Stratix II GX Architecture
shows which
Figure 2–31
Stratix II GX
Stratix II GX
Transceiver
Transceiver
Block
Block
2–37