EP1S10F780C5N Altera, EP1S10F780C5N Datasheet - Page 37
![IC STRATIX FPGA 10K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S10F780C5N
Manufacturer Part Number
EP1S10F780C5N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F780C5N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780C5N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 37 of 276
- Download datasheet (4Mb)
Altera Corporation
July 2005
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
occurs or just read the don’t care bits. Single-port memory supports non-
simultaneous reads and writes, but the q[] port will output the data once
it has been written to the memory (if the outputs are not registered) or
after the next rising edge of the clock (if the outputs are registered). For
more information, see
Stratix & Stratix GX Devices
Figure 2–13
TriMatrix memory.
Figure 2–13. Simple Dual-Port & Single-Port Memory Configurations
Note to
(1)
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
Figure
Simple Dual-Port Memory
Single-Port Memory (1)
shows these different RAM memory port configurations for
2–13:
data[ ]
wraddress[ ]
wren
inclocken
inaclr
data[ ]
address[ ]
wren
inclocken
inaclr
inclock
inclock
Chapter 2, TriMatrix Embedded Memory Blocks in
of the
Stratix Device Handbook, Volume
Stratix Device Handbook, Volume 1
rdaddress[ ]
outclocken
outclocken
outclock
outclock
outaclr
outaclr
rden
q[ ]
q[ ]
Stratix Architecture
2.
2–23
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