EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 2
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EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–2
Cyclone IV Device Handbook, Volume 1
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Cyclone IV GX devices offer up to eight high-speed transceivers that provide:
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Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)
Gen 1:
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Cyclone IV GX devices offer a wide range of protocol support:
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Data rates up to 3.125 Gbps
8B/10B encoder/decoder
8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer
(PCS) interface
Byte serializer/deserializer (SERDES)
Word aligner
Rate matching FIFO
TX bit slipper for Common Public Radio Interface (CPRI)
Electrical idle
Dynamic channel reconfiguration allowing you to change data rates and
protocols on-the-fly
Static equalization and pre-emphasis for superior signal integrity
150 mW per channel power consumption
Flexible clocking structure to support multiple protocols in a single transceiver
block
×1, ×2, and ×4 lane configurations
End-point and root-port configurations
Up to 256-byte payload
One virtual channel
2 KB retry buffer
4 KB receiver (Rx) buffer
PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)
Gigabit Ethernet (1.25 Gbps)
CPRI (up to 3.072 Gbps)
XAUI (3.125 Gbps)
Triple rate serial digital interface (SDI) (up to 2.97 Gbps)
Serial RapidIO (3.125 Gbps)
Basic mode (up to 3.125 Gbps)
V-by-One (up to 3.0 Gbps)
DisplayPort (2.7 Gbps)
Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)
OBSAI (up to 3.072 Gbps)
Chapter 1: Cyclone IV FPGA Device Family Overview
© December 2010 Altera Corporation
Cyclone IV Device Family Features