EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 148
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Quantity
Price
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PLLs & Clock Networks
Figure 4–51. Stratix GX Enhanced PLL
Notes to
(1)
(2)
(3)
4–82
Stratix GX Device Handbook, Volume 1
CLK0
CLK1
External feedback is available in PLLs 5 and 6.
This external output is available from the g0 counter for PLLs 11 and 12.
These counters and external outputs are available in PLLs 5 and 6.
Figure
Switch-Over
Circuitry
Clock
4–51:
FBIN
/n
(1)
Δt
Enhanced PLLs
Stratix GX devices contain up to four enhanced PLLs with advanced
clock management features.
enhanced PLL.
Phase Frequency
Detector
PFD
Charge
Pump
VCO Phase Selection
Selectable at Each
PLL Output Port
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
Spectrum
Δt
Spread
Filter
Loop
/m
From Adjacent PLL
VCO
Figure 4–51
8
Post-Scale
Counters
shows a diagram of the
/g0
/g1
/g2
/g3
/e0
/e1
/e2
/e3
/l0
/l1
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Programmable
Time Delay on
Each PLL Port
4
4
Altera Corporation
February 2005
I/O Buffers (2)
to I/O or general
routing
Regional
Clocks
Global
Clocks
I/O Buffers (3)
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