EP2C70F672C6 Altera, EP2C70F672C6 Datasheet - Page 158
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EP2C70F672C6
Manufacturer Part Number
EP2C70F672C6
Description
IC CYCLONE II FPGA 70K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C70F672C6
Number Of Logic Elements/cells
68416
Number Of Labs/clbs
4276
Total Ram Bits
1152000
Number Of I /o
422
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-5°C ~ 50°C
Package / Case
672-FBGA
For Use With
P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C70F672C6
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2C70F672C6N
Manufacturer:
ALTERA
Quantity:
852
Part Number:
EP2C70F672C6N
Manufacturer:
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Duty Cycle Distortion
Figure 5–9. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–68
Cyclone II Device Handbook, Volume 1
clk
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal, or caused by the clock input buffer, or
different input I/O standard, does not transfer to the output signal.
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
(Figure
DFF
D
5–10). Therefore, any distortion on the input
Q
(Figure
5–9). Therefore, any DCD
Altera Corporation
output
February 2008