EP1SGX10DF672C7N Altera, EP1SGX10DF672C7N Datasheet - Page 228
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C7N
Manufacturer Part Number
EP1SGX10DF672C7N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX10DF672C7N
Manufacturer:
ALTERA10
Quantity:
61
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Timing Model
6–26
Stratix GX Device Handbook, Volume 1
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
Stratix GX device internal timing microparameters for LEs, IOEs,
TriMatrix
interconnects.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
CLR
PRE
CLKHL
SU
H
CO
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKHL
Table 6–36. LE Internal Timing Microparameter Descriptions
Table 6–37. IOE Internal Timing Microparameter Descriptions
Symbol
Symbol
™
memory structures, DSP blocks, and MultiTrack
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinational LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinational output
Column input pin to IOE combinational output
Row IOE data input to combinational output pin
Column IOE data input to combinational output pin
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Tables 6–36
Parameter
Parameter
through
6–42
Altera Corporation
describe the
June 2006
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