EP2S15F672I4N Altera, EP2S15F672I4N Datasheet - Page 51
EP2S15F672I4N
Manufacturer Part Number
EP2S15F672I4N
Description
IC STRATIX II FPGA 15K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F672I4N
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
366
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S15F672I4N
Manufacturer:
ALTERA
Quantity:
220
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Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
May 2007
Optional Serial Shift
Register Outputs to
interface block
Next DSP Block
in the Column
From the row
Register Inputs from
Optional Serial Shift
Previous DSP Block
PRN
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Q
Q
Q
Q
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Saturate
Saturate
Saturate
Saturate
Round/
Round/
Round/
Round/
Q1.15
Q1.15
Q1.15
Q1.15
Multiplier Block
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Adder Output Block
Optional Pipline
Register Stage
Accumulator
Accumulator
Optional Stage Configurable
as Accumulator or Dynamic
Subtractor/
Subtractor/
Adder/
Adder/
2
1
Adder/Subtractor
Stratix II Device Handbook, Volume 1
Saturate
Saturate
Multipliers Together
Round/
Round/
Q1.15
Q1.15
Summation Stage
for Adding Four
Summation
Block
Adder
Interconnect
to MultiTrack
Multiplexer
Selection
Output
Stratix II Architecture
ENA
D
CLRN
Q
2–43
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