EP20K200EFC484-2 Altera, EP20K200EFC484-2 Datasheet - Page 75
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EP20K200EFC484-2
Manufacturer Part Number
EP20K200EFC484-2
Description
IC APEX 20KE FPGA 200K 484-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K200EFC484-2
Number Of Logic Elements/cells
8320
Number Of Labs/clbs
832
Total Ram Bits
81920
Number Of I /o
376
Number Of Gates
404000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K200EFC484-2
Manufacturer:
ALTERA
Quantity:
319
Company:
Part Number:
EP20K200EFC484-2N
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP20K200EFC484-2X
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ALTERA
Quantity:
1 238
Company:
Part Number:
EP20K200EFC484-2X
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ALTERA
Quantity:
513
Company:
Part Number:
EP20K200EFC484-2XN
Manufacturer:
ALTERA
Quantity:
3 000
Altera Corporation
t
t
t
t
t
t
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 38. APEX 20KE External Timing Parameters
Symbol
Setup time with global clock at IOE input register
Hold time with global clock at IOE input register
Clock-to-output delay with global clock at IOE output register
Setup time with PLL clock at IOE input register
Hold time with PLL clock at IOE input register
Clock-to-output delay with PLL clock at IOE output register
Note to
(1)
Tables 38
t
t
t
TCH
TCL
TCLRP
TPREP
TESBCH
TESBCL
TESBWP
TESBRP
F1-4
F5-20
F20+
Table 36. APEX 20KE Routing Timing Microparameters
Table 37. APEX 20KE Functional Timing Microparameters
Symbol
Symbol
These parameters are worst-case values for typical applications. Post-compilation
timing simulation and timing analysis are required to determine actual worst-case
performance.
Table
and
36:
39
Fanout delay using Local Interconnect
Fanout delay estimate using MegaLab Interconnect
Fanout delay estimate using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear Pulse Width
LE preset pulse width
Clock high time for ESB
Clock low time for ESB
Write pulse width
Read pulse width
Clock Parameter
describe the APEX 20KE external timing parameters.
APEX 20K Programmable Logic Device Family Data Sheet
Note (1)
Parameter
Parameter
Note (1)
C1 = 10 pF
C1 = 10 pF
Conditions
75