EP3C55F780I7N Altera, EP3C55F780I7N Datasheet - Page 34
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EP3C55F780I7N
Manufacturer Part Number
EP3C55F780I7N
Description
IC CYCLONE III FPGA 55K 780 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C55F780I7N
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
377
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2554
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C55F780I7N
Manufacturer:
ALTERA
Quantity:
310
Company:
Part Number:
EP3C55F780I7N
Manufacturer:
ALTERA42
Quantity:
202
Part Number:
EP3C55F780I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–24
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side
Cyclone III Device Handbook, Volume 2
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
(2)
DDR SDRAM
Standard
Memory
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
Table 1–33
devices.
I/O Standard
lists the transmitter channel-to-channel skew specifications for Cyclone III
Lead
1025
1010
1010
1040
1180
1010
1160
1040
1190
1076
1061
1061
1092
1239
1061
1218
790
870
750
860
780
830
915
880
910
961
924
956
Column I/Os (ps)
C6
C7
C8
A7
I7
380
490
320
350
410
510
410
545
340
380
450
570
440
600
360
410
490
630
431
572
357
399
473
599
462
630
378
431
Lag
Lead
1025
1010
1010
1040
1180
1010
1160
1040
1190
1076
1061
1061
1092
1239
1061
1218
790
870
750
860
780
830
915
880
910
961
924
956
Row I/Os (ps)
Chapter 1: Cyclone III Device Data Sheet
Lag
380
490
320
350
410
510
410
545
340
380
450
570
440
600
360
410
490
630
431
572
357
399
473
599
462
630
378
431
(Note 1)
© January 2010 Altera Corporation
Wraparound Mode (ps)
1015
1125
1110
1010
1110
1140
1280
1110
1260
1140
1290
1061
1176
1024
1161
1056
1161
1192
1339
1161
1318
Lead
890
970
850
960
880
930
980
Switching Characteristics
(Part 1 of 2)
480
590
420
450
510
610
510
645
440
480
550
670
540
700
460
510
590
730
531
672
457
499
573
699
562
730
478
531
Lag