EP1S10F484C7 Altera, EP1S10F484C7 Datasheet - Page 90
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7
Manufacturer Part Number
EP1S10F484C7
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1100
Available stocks
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EP1S10F484C7
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PLLs & Clock Networks
2–76
Stratix Device Handbook, Volume 1
Figure 2–43. Regional Clocks
Fast Regional Clock Network
In EP1S25, EP1S20, and EP1S10 devices, there are two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins that can
connect to fast regional clock networks (see
larger devices, there are two fast regional clock networks within each
half-quadrant (see
clock networks. All devices have eight FCLK pins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. This signal is
driven via the I/O interconnect. The fast regional clock networks can also
be driven from internal logic elements.
RCLK[1..0]
RCLK[4..5]
CLK[3..0]
Figure
2–45). Dual-purpose FCLK pins drive the fast
RCLK[6..7]
RCLK[2..3]
CLK[7..4]
RCLK[12..13]
RCLK[11..10]
CLK[15..12]
Figure
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
2–44). In EP1S30 and
Altera Corporation
CLK[11..8]
RCLK[14..15]
July 2005
RCLK[9..8]
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