EP20K200EQC240-3 Altera, EP20K200EQC240-3 Datasheet - Page 9
![IC APEX 20KE FPGA 200K 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP20K200EQC240-3
Manufacturer Part Number
EP20K200EQC240-3
Description
IC APEX 20KE FPGA 200K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K200EQC240-3
Number Of Logic Elements/cells
8320
Number Of Labs/clbs
832
Total Ram Bits
81920
Number Of I /o
168
Number Of Gates
404000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1095
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K200EQC240-3
Manufacturer:
ALTERA
Quantity:
12
Part Number:
EP20K200EQC240-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Functional
Description
Figure 1. APEX 20K Device Block Diagram
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Clock Management Circuitry
ClockLock
IOE
IOE
Product Term
Product Term
APEX 20K devices incorporate LUT-based logic, product-term-based
logic, and memory into one device. Signal interconnections within
APEX 20K devices (as well as to and from device pins) are provided by the
FastTrack
channels that run the entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a register that can be used as either an input
or output register to feed input, output, or bidirectional signals. When
used with a dedicated clock pin, these registers provide exceptional
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,
66-MHz PCI compliance; JTAG BST support; slew-rate control; and
tri-state buffers. APEX 20KE devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,
3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V
AGP I/O standards.
The ESB can implement a variety of memory functions, including CAM,
RAM, dual-port RAM, ROM, and FIFO functions. Embedding the
memory directly into the die improves performance and reduces die area
compared to distributed-RAM implementations. Moreover, the
abundance of cascadable ESBs ensures that the APEX 20K device can
implement multiple wide memory blocks for high-density designs. The
ESB’s high speed ensures it can implement small memory blocks without
any speed penalty. The abundance of ESBs ensures that designers can
create as many different-sized memory blocks as the system requires.
Figure 1
Memory
Memory
LUT
IOE
LUT
IOE
shows an overview of the APEX 20K device.
®
Product Term
Product Term
Interconnect—a series of fast, continuous row and column
Memory
Memory
LUT
LUT
IOE
IOE
APEX 20K Programmable Logic Device Family Data Sheet
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
FastTrack
Interconnect
IOE
IOE
LUT
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
9