EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 59

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–20. Cyclone III LS Devices PLL Specifications
© December 2009
f
output)
t
t
t
t
t
t
t
t
t
t
f
Notes to
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(2) With 100-MHz scanclk frequency.
(3) Peak-to-peak jitter with a probability level of 10
(4) V
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
(6) The V
f
OUT_EXT
OUTDUTY
LOCK
DLOCK
OUTJITTER_PERIOD_DEDC LK
OUTJITTER_CCJ _DEDCLK
OUTJITTER_PERIOD_IO
OUTJITTER_CCJ _IO
PLL_PSERR
ARESET
CONF IGPLL
SC ANC LK
OUT
(to global clock)
standard.
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
than 200 ps.
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
CC D_P LL
(external clock
(1)
Table
CO
Symbol
must be connected to V
frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V
(3)
(3)
2–20:
(3)
Altera Corporation
(3)
PLL output frequency
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when set to
50%)
Time required to lock from end of device
configuration
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter F
F
Dedicated clock output cycle-to-cycle jitter
F
F
Regular I/O period jitter F
F
Regular I/O cycle-to-cycle jitter F
F
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
scanclk frequency
OUT
OUT
OUT
OUT
OUT
CC INT
< 100 MHz
≥ 100 MHz
< 100 MHz
< 100 MHz
< 100 MHz
through the decoupling capacitor and ferrite bead.
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
Parameter
(Note 4)
OUT
≥ 100 MHz
OUT
(Part 2 of 2) (Preliminary)
≥ 100 MHz
OUT
≥ 100 MHz
Min
426
379
—
45
—
—
—
—
—
—
—
—
—
—
—
10
—
—
Cyclone III Device Handbook, Volume 2
Typ
3.5
(2)
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
VC O
402.5
Max
450
450
300
300
650
650
±50
100
55
30
30
75
75
—
—
specification.
1
1
scanclk
cycles
MHz
MHz
MHz
MHz
Unit
mUI
mUI
mUI
mUI
ms
ms
ps
ps
ps
ps
ps
ns
%
2–15
C O